ASIC/SoC Design & Verification Engineer (Remote, Contract)

About OpenTrain

OpenTrain is the #1 platform for people building careers in AI training and data labeling. We help engineers turn domain expertise into durable freelance work by centralizing projects, tracking contributions, and making it easy to apply and grow a professional portfolio.

OpenTrain AI is the hiring and contracting organization for this role; creating an OpenTrain account is free and gives you access to projects across the industry.

About AI training work

AI training (data labeling and human feedback) is the human side of building modern models. Engineers prepare realistic problems and evaluate model outputs so AI systems learn correct reasoning and hardware engineering judgment.

This role places experienced ASIC/SoC practitioners at the cutting edge of that work: you will translate real engineering scenarios into problems and verification collateral that test how well models understand and perform chip-design tasks.

The role

As an ASIC/SoC Design & Verification Engineer you will design realistic chip-engineering problems from your own hands-on experience, produce reference solutions (RTL, testbenches, and supporting materials), and evaluate AI model responses against those problems. You will work with other engineers to keep difficulty and rigor consistent across work items.

What you'll do

• Create chip engineering problems drawn from your ASIC or SoC design & verification experience.
• Build complete reference solutions including RTL, testbenches, and documentation for reproducible evaluation.
• Evaluate and rate AI model outputs against the reference solutions, documenting where model reasoning or implementations succeed or fail.
• Collaborate with other engineers to align problem difficulty, verification standards, and evaluation criteria.

Requirements

You must have hands-on ASIC or SoC design and/or functional verification experience and strong written communication. Work is independent and technical accuracy is essential.

• Hands-on ASIC or SoC design or functional verification experience (required).
• Strong fluency in SystemVerilog or Verilog (required).
• Experience writing RTL, verification testbenches, or other verification collateral.
• Familiarity with EDA or open-source tools such as VCS, Xcelium, Questa, Verilator, CocoTB, Yosys, or OpenROAD.
• Solid understanding of subsystem and SoC concerns (handshaking, backpressure, clock domains, multi-module dataflow).
• Deep experience in one or more: RTL design, IP integration, UVM, SVA, formal verification, timing closure, synthesis optimization, or analog/mixed-signal verification.
• Ability to evaluate AI model outputs on technical engineering tasks and explain breakdowns clearly.

Logistics, compensation, and expectations

This is a contractor, part-time role requiring at least 20+ hours per week. Work is remote and available to applicants in the United States (English required).

Pay is hourly: $70–$100 per hour (structured as PAY_PER_HOUR).

• Employment type: Contractor, Part-time.
• Time requirement: 20+ hours/week.
• Location: United States (remote).
• Language: English.

Who should apply and how it works

Apply if you are an intermediate or senior ASIC/SoC engineer who enjoys translating real engineering challenges into reproducible problems and judging model outputs with technical rigor. This role is ideal for people who can write clear verification collateral and work independently while coordinating with an engineering team to maintain standards.

To apply, create a free OpenTrain account, complete your profile, and submit a short summary of your ASIC/SoC experience. If available, include links or references to sample RTL, testbenches, or verification artifacts to help evaluate fit.