RTL and Design Verification Engineer

About OpenTrain

OpenTrain is the #1 platform for people building careers in AI training and data labeling. We help contributors find and grow work that shapes how modern AI systems learn — offering flexible, remote opportunities and tools to build a durable freelance career.

OpenTrain AI is the hiring and contracting organization for this role. You will work directly on evaluation tasks that help engineers improve chip design and verification workflows used in state-of-the-art silicon development.

Why This AI-Training Work Matters

AI training here means human expertise applied to technical evaluation tasks that teach and test models and workflows. In this project, that expertise is chip design and verification: your reviews and debug reports help improve automated evaluation, tooling, and model-assisted design flows.

Many contributors choose this kind of work for its remote flexibility, technical challenge, and the opportunity to influence how advanced tools for chip design behave.

The Role

We are recruiting senior chip design and verification experts on two technical tracks: RTL design and design verification. Both tracks require deep technical judgment, clear written documentation, and collaborative problem-solving across engineering workflows.

Tasks include reviewing RTL or verification code and artifacts, debugging issues with simulation logs and waveform viewers, and producing documentation and coverage-focused reports that feed back into verification pipelines.

What You'll Do

Work on practical evaluation and improvement tasks across digitalsilicon workflows. Deliver clear findings, testbench components, and reproducible debug artifacts that help drive coverage closure and verification quality.

• Review RTL or verification work for correctness, clarity, and technical tradeoffs.
• Debug design issues using simulation logs, waveform tools, and standard EDA flows.
• Build or improve verification components, scoreboards, reference models, or regression flows.
• Contribute verification plans, design documentation, and debug reports.
• Apply strong reasoning to architecture, implementation, and coverage questions in silicon workflows.

Requirements

Candidates must have substantial hands-on experience with digital RTL or verification tasks and be able to communicate technical tradeoffs clearly to engineering peers and reviewers.

• 3 to 10 years of experience in digital RTL design or design verification.
• Strong Verilog, SystemVerilog, or UVM fluency (track-dependent).
• Experience with ASIC design flows, verification infrastructure, and common EDA tools.
• Familiarity with digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, and bus protocols.
• Ability to produce clear documentation, verification plans, and debug reports.
• Availability for 20+ hours/week; full-time preferred with high availability expected.

Helpful Background (Nice to Have)

These skills are not required but align well with the project work and may increase impact and compensation.

• Experience with AMBA protocols (AXI, AHB, APB).
• Prior work on CPU, GPU, ML accelerators, networking, memory subsystems, PCIe, high-speed IO, or SoC interconnects.
• Exposure to formal verification, SV/UVM-based verification, coverage-driven regression, timing analysis, CDC, DFT-aware design, or low-power techniques.
• Familiarity with LLM-based tools for chip design or verification workflows is a plus.

Location, Schedule & Compensation

This is a remote contract role open to candidates located in the United States or Canada. The target engagement is about 3+ months, starting in late April; ongoing work may be available for high-performing contributors.

Compensation is hourly. Pay range: $100 to $175 USD per hour. Employment types: contractor, part-time (20+ hrs/week); full-time schedules with high availability are preferred.

Who Should Apply and How It Works

Apply if you are an experienced RTL or verification engineer who enjoys clear technical writing, reproducible debugging, and collaborating to close verification gaps. You do not need prior AI-training experience — domain expertise and an ability to document and reason about silicon workflows are the core requirements.

OpenTrain provides the contract, project scope, and feedback loops that let you contribute remotely and build profile credits for future opportunities. If this role fits your skills and availability, submit your profile and application through OpenTrain to be considered.