Freelancer Overview
I have done my M.E. in Embedded Systems at BITS Pilani with a B.E. (Hons.) in Electronics and Communication Engineering, graduating with a CGPA of 8.76. I secured a rank of 256 in GATE EC out of 70k+ students all over India, appearing a year ahead of schedule in my third year of B.E. My technical work spans embedded systems, Edge AI, wireless sensing, hardware design, and AI training data preparation, with hands-on experience across the full stack from signal acquisition and dataset construction to model training, validation, and deployment on constrained hardware.
I co-authored a comprehensive survey published in IEEE Internet of Things Journal in 2026 as co-first author, analyzing 65+ ML models for Wi-Fi CSI-based sensing across hardware, signal processing, and edge deployment — working alongside Fellows of IEEE from MBZUAI Abu Dhabi and Nanyang Technological University Singapore. I completed a six-month Design Verification internship at Tenstorrent using SystemVerilog, UVM, and Synopsys VCS, and received a Core DV Lead return offer which I declined to pursue graduate research. I currently work at the BITS Pilani Innovation Centre IoT Lab deploying and optimizing AI inference on Kria KV260 (FPGA), Jetson Xavier NX, Jetson Nano, and Jetson Orin Nano Super, with experience in TensorRT optimization, Vitis AI quantization, and real-time inference pipeline design.
I have hands-on experience in AI training data preparation, annotation review, and validation for remote-sensing object detection, specifically SAR ship detection. My recent work involved author-reviewed labeling of more than 500 ship targets in Sentinel-1 SAR scene crops, including careful inspection of dense traffic, open-water ships, near-shore clutter, ambiguous targets, and false-alarm-prone regions. I have worked with bounding-box annotations, crop-level audit design, label quality control, and evaluation metrics including TP, FP, FN, precision, recall, F1, and missed-target analysis. This work is directly connected to end-to-end model validation and deployment — I have experience preparing datasets for YOLO-style detection, reviewing model outputs against human labels, analyzing cascade and gating failures, and supporting hardware-aware validation for SAR ship-detection systems, giving me a strong understanding of both the data-quality side and the model-performance side of AI training pipelines.
My programming languages include Python, C, and C++, with additional experience in MATLAB, Assembly (x86), and Verilog/SystemVerilog. I am comfortable working across the hardware-software boundar: from low-level circuit design and FPGA fabric programming to high-level model training and dataset pipeline construction.
Geospatial Tiled Imagery
Bounding Box